diff --git a/board/warp/warp.c b/board/warp/warp.c
index 0bc0a6a..b1b528a 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -62,7 +62,7 @@
 }
 
 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
-	{USDHC2_BASE_ADDR},
+	{USDHC2_BASE_ADDR, 0, 0, 0, 1},
 };
 
 int board_mmc_getcd(struct mmc *mmc)
diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc
index 7e71387..29cc661 100644
--- a/doc/README.fsl-esdhc
+++ b/doc/README.fsl-esdhc
@@ -20,5 +20,3 @@
 	- CONFIG_SYS_FSL_ESDHC_BE
 		ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
 		by ESDHC IP's endian mode or processor's endian mode.
-
-	- CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 50ed80a..3abd2d3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -673,10 +673,6 @@
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
 
-#ifdef CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
-	esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-#endif
-
 	if (priv->vs18_enable)
 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
 
diff --git a/include/configs/warp.h b/include/configs/warp.h
index afe3eae..e3f79b1 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -23,7 +23,6 @@
 
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 #define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 #define CONFIG_SUPPORT_EMMC_BOOT
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index e261d02..baf8799 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3208,7 +3208,6 @@
 CONFIG_SYS_FSL_ESDHC_ADDR
 CONFIG_SYS_FSL_ESDHC_BE
 CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
-CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
 CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
 CONFIG_SYS_FSL_ESDHC_LE
 CONFIG_SYS_FSL_ESDHC_NUM